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- Keithley Applications
- Posts: 1263
- Joined: October 15th, 2010, 10:35 am
- Country: United States
Bit11 will reveal the interlock state.
Bit11 = logic 0 state = interlock not asserted; source output prevented
Bit11 = logic 1 state = interlock asserted; source output permitted
If you just want to read the present state of the interlock, read the condition register of this register set:
print(bit.bitand(status.measurement.condition, 2048)) -- logical AND with 2048
print(bit.test(status.measurement.condition, 12)) --one based bit position
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