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DPO7000 series internal architecture

DPO70000SX, DPO/MSO70000, DPO7000 Series, DPO/MSO5000 Series
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Joined: November 7th, 2018, 11:59 am
Country: Czech Republic

DPO7000 series internal architecture

Post by mhudlicka » November 8th, 2018, 12:51 am

Hi all,

I'm trying to get the best performance from my DPO7354C oscilloscope. One could calibrate out most of systematic errors coming from different ADC gains, timing errors etc. provided some statistical information about the sampled signal is a priori known and the internal ADC architecture is roughly known. Such methods can be found in scientific literature. The SPC (signal path compensation) is able to remove some of the errors and then there are not so many unwanted spurs in the output spectrum (but this is done for a general signal and is not ideal). I believe one could do much more with appropriate compensation techniques applied off-line so that the vertical resolution can be much better, timing errors are negligible and the spurs coming from various internal imperfections can be calibrated out to enhance the SFDR. The idea is to make a superior sampler for certain class of signals from the mid-class DPO7354C scope by applying offline signal processing of the acquired waveform.

What I know is that DPO7354C uses 4 channels with shared clock (i.e. 40 GS/S at 1 channel, 20 GS/s at 2 channels or 10 GS/s at 4 channels). I also assume each channel comprises of many time-interleaved ADCs in a pipeline structure to get a high bandwidth. There are techniques to guess the number of sub-ADCs at any particular channel and to guess the clock-interleaving scheme, however with DPO7354C I failed with application of known methods and the number of sub-ADCs at each channel is ambiguous (in other words, methods working for architectures from other vendors seem to fail here). It seems there must be some other internal blocks which introduce additional spurs (maybe the DSP trick which makes 3.5 GHz bandwidth from the basically 2.5 GHz bandwidth oscilloscope?). I also assume the Asynchronous time interleaving is not yet applied in this oscilloscope series.

Could someone give me a reference to particular patent applications or share your experience? The DPO7000 series is quite old and I believe no secret would be compromised by disclosing some of the internal details.

Regards, Martin

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Joined: January 7th, 2019, 1:34 am
Country: United States

Re: DPO7000 series internal architecture

Post by Palpopa » January 8th, 2019, 3:33 am

Is there no documentation on DPO7000 series architecture floating around? That's kind of odd considering how old it is.

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